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CMOS Static RAM 1 Meg (64K x 16-Bit)
Features
64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times - Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTLcompatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Commercial and industrial product available in 44-pin Plastic SOJ package and 44-pin TSOP package
IDT71016

Description
The IDT71016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71016 has an output enable pin which operates as fast as 7ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71016 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71016 is packaged in a JEDEC standard 44-pin Plastic SOJ and 44-pin TSOP Type II.

Functional Block Diagram
OE Output Enable Buffer
A0 - A15
Address Buffers
Row / Column Decoders
I/O 15 Chip Enable Buffer Sense Amps and Write Drivers 8 Low Byte I/O Buffer 8 8 High Byte I/O Buffer 8
,
CS
I/O 8
WE
Write Enable Buffer
64K x 16 Memory Array
16
I/O 7
I/O 0
BHE Byte Enable Buffers BLE 3210 drw 01
JANUARY 2004
1
(c)2004 Integrated Device Technology, Inc. DSC-3210/8
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A4 A3 A2 A1 A0 CS I/O 0 I/O 1 I/O 2 I/O 3 VCC VSS I/O 4 I/O 5 I/O 6 I/O 7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO44-1 SO44-2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 VSS VCC I/O 11 I/O 10 I/O 9 I/O 8 NC A8 A9 A10 A11 NC
3210 drw 02
Pin Descriptions
A0 - A15 CS WE OE BHE BLE I/O0 - I/O15 VCC VSS Address Inputs Chip Select Write Enable Output Enable High Byte Enable Low Byte Enable Data Input/Output 5.0V Power Ground Input Input Input Input Input Input I/O Pwr Gnd
3210 tbl 01
,
SOJ/TSOP Top View
Truth Table (1)
CS H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L H L L L H X H BHE X H L L L H L X H I/O0 - I/O7 High-Z DATAOUT High-Z DATAOUT DATAIN DATAIN High-Z High-Z High-Z I/O8 - I/O15 High-Z High-Z DATAOUT DATAOUT DATAIN High-Z DATAIN High-Z High-Z Function Deselected - Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Outputs Disabled Outputs Disabled
3210 tbl 02
NOTE: 1. H = VIH, L = VIL, X = Don't care.
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IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM (2) TA TBIAS TSTG PT IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 1.25 50 Unit V
o o
Recommended Operating Temperature and Supply Voltage
Grade Commercial Temperature 0C to +70C -40C to +85C GND 0V 0V VCC 5.0V 10% 5.0V 10%
3210 tbl 04
C C C
Industrial
o
Recommended DC Operating Conditions
Symbol VCC Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
W mA
Max. 5.5 0 VDD +0.5 0.8
Unit V V V V
GND
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
3210 tbl 03
VIH VIL
____
3210 tbl 05 NOTE: 1. VIL (min.) = -1.5V for pulse width less than tRC/2, once per cycle.
Capacitance
Symbol CIN CI/O
(TA = +25 C, f = 1.0MHz, SOJ Package)
Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
(VCC = 5.0V 10%, Commercial and Industrial Temperature Range)
Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
___ ___ ___
DC Electrical Characteristics
3210 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
Max. 5 5 0.4
___
Unit A A V V
3210 tbl 07
2.4
DC Electrical Characteristics(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC-0.2V)
71016S12 Symbol ICC ISB Parameter Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VCC = Max., F = fMAX(2) Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VCC = Max., f = 0(2) VIN < VLC or VIN > VHC Com'l. 210 60 10 Ind. 210 60 10 71016S15 Com'l. 180 50 10 Ind. 180 50 10 71016S20 Com'l. 170 45 10 Ind. 170 45 10 Unit mA mA mA
ISB1
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
3210 tbl 08
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IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 1.5ns 1.5V 1.5V See Figure 1, 2 and 3
3210 tbl 09
AC Test Loads
5V 480
5V 480 DATA OUT
DATA OUT 30pF* 255
5pF*
255
3210 drw 04
3210 drw 03
,
,
*Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7 tAA, tACS (Typical, ns) 5 4 3 2 1
* * * * * *
*
6
,
CAPACITANCE (pF)
3210 drw 05
8 20 40 60 80 100 120 140 160 180 200
Figure 3. Output Capacitive Derating
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IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol READ CYCLE tRC tAA tACS tCLZ
(1)
(VCC = 5.0V 10%, Commercial and Industrial Range)
71016S12 71016S15 Min. Max. 71016S20 Min. Max. Unit Min. Max.
Parameter
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select High to Output in High-Z Output Enable Low to Output Valid Output Enable Low to Output in Low-Z Output Enable High to Output in High-Z Output Hold from Address Change Byte Enable Low to Output Valid Byte Enable Low to Output in Low-Z Byte Enable High to Output in High-Z
12
____ ____
____
15
____ ____
____
20
____ ____
____
ns ns ns ns ns ns ns ns ns ns ns ns
12 12
____
15 15
____
20 20
____
4
____
5
____
5
____
tCHZ(1) tOE tOLZ (1) tOHZ (1) tOH tBE tBLZ(1) tBHZ(1) WRITE CYCLE tWC tAW tCW tBW tAS tWR tWP tDW tDH tOW
(1)
6 7
____
6 8
____
8 10
____
____
____
____
0
____
0
____
0
____
6
____
6
____
8
____
4
____
4
____
5
____
7
____
8
____
10
____
0
____
0
____
0
____
6
6
8
Write Cycle Time Address Valid to End of Write Chip Select Low to End of Write Byte Enable Low to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable High to Output in Low-Z Write Enable Low to Output in High-Z
12 9 9 9 0 0 9 7 0 1
____
____ ____ ____ ____ ____ ____ ____ ____ ____
15 10 10 10 0 0 10 8 0 1
____
____ ____ ____ ____ ____ ____ ____ ____ ____
20 12 12 12 0 0 12 10 0 1
____
____ ____ ____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns ns
3210 tbl 10
____
____
____
tWHZ(1)
6
6
8
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
3210 drw 06
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW.
,
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IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
tRC ADDRESS tAA tOH
OE
tOE tOHZ
(3)
,
CS
tCLZ
(3)
tOLZ tACS (2)
(3)
tCHZ
(3)
BHE, BLE
tBE tBLZ DATAOUT
(3) (2)
tBHZ DATA OUT VALID
(3)
NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured 200mV from steady state.
3210 drw 07
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC ADDRESS tAW CS tCW BHE , BLE tWR WE tAS tWHZ DATAOUT PREVIOUS DATA VALID
(3) (5)
(2)
tCHZ
(5)
tBW
(5)
tBHZ
tWP
tOW tDW tDH
(5)
DATA VALID
,
3210 drw 08
DATAIN
DATAIN VALID
NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state.
6.42 6
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC ADDRESS tAW CS
tAS tBW
tCW (2)
BHE , BLE tWP WE tWR
,
tDH
DATAOUT tDW DATAIN DATAIN VALID
3210 drw 9
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
tWC ADDRESS tAW CS tAS BHE , BLE tWP WE tWR tCW
(2)
tBW
DATAOUT tDW DATAIN DATAIN VALID
3210 drw 10
tDH
,
NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state.
6.42 7
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71016 Device Type S Power XX Speed XXX Package X X Process/ Temperature Range Blank I G Y PH 12 15 20 Commercial (0C to +70C) Industrial (-40C to +85C) Restricted hazardous substance device. 400-mil SOJ (SO44-1) 400-mil TSOP Type II (SO44-2)
Speed in nanoseconds
3210 drw 11
6.42 8
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
7/30/99 8/5/99 Pg. 3 Pg. 5 Pg. 6 Pg. 7 Pg. 8 8/13/99 9/30/99 08/09/00 02/01/01 01/30/04 Pg. 9 Pg. 3, 5, 8 Updated to new format Expressed commercial and industrial ranges on DC Electrical table Removed Icc, ISB, and ISB1 values for S12 industrial speed Expressed commercial and industrial ranges on AC Electrical table Changed footnote #2 to commercial temperature only Revised footnotes on Write Cycle No. 1 diagram Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Removed SCD 2752 footnote Added commercial only for 12ns speed Added Datasheet Document History Added 12ns industrial temperature speed grade offering Not recommended for new designs Removed "Not recommended for new designs" Added "Restricted hazardous substance device" to order information.
Pg. 8
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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